Yamaha CL3 Service Manual page 303

H G
■ BLOCK DIAGRAM 003 (CL3/CL1)
CPU
IC103
(5P)
+3.3D
RESET
(3.0V)
BT501
USB
IC203 (5P) +5D
USB
Power
+3.3D
Switch
OSC
IC201
25MHz
(48P)
+3.3D
X404
USB
USB
Hub
DS US
CN203
Xtal
12MHz
X201
+3.3D
IC106 (5P)
RESET
(2.9V)
DC-DC
IC105 (25P)
CN601 (180P)
CN103 (5P)
CN101 (180P)
DSP
See Page 4
28CA1-2001089459-3
F E
+3.3D
IC205 (56P)
+3.3D
FlashROM
512Mbit
(MAC Address Inside)
6 1 t i b
CPU Bus
Wired OR
+1.8D
/SYSRES IC301, 302
IC104 (8P)
DDR2-SDRAM
1Gbit x2
+3.3D +3.3D +1.8D +1.2D
IC503 (5P)
+3.3B
Battery Backup
& Check
PORT
(Comparator, Diode, FET)
D501, 502, FT501,510
+3.3B
CPU
IC502
RTC
I2C
SH7724
(10P)
Xtal IC101
32.768KHz
X501
CPU Core : 489.6MHz
+3.3D
DDR2-SDRAM : 163.2MHz
BUS : 81.6MHz
10/100Base
RMII
PHY
IC402 (33P)
PORT USB FSI SPI
+1.2D
+1.8D
Ethernet /RES_IN PORT USB TDM Fs, 64Fs SPI
(2ch/line) (Master Clock)
IN : CAUTIONS(DCMS), ...
OUT : PORT RESETS, ...
D
+3.3D
CPLD
+3.3D
IC202 (100P)
IC203 (20P)
IC204 (44P)
Address Decode
Wait Control
MRAM E-Bus
E-Bus BUSY
1Mbit Controller
IRQ OR
6 1 t i b 8bit 8bit
32bit
+3.3D
OSC
X101
27.2MHz
OSC
X401
48MHz
+3.3D +3.3D
CKO BUFFER
IC201 (8P)
/WAIT
IRQ
PORT
LCDC
IRQ
I2C SCI
IC602-607
+3.3D
(20P)
16bit
I2C SCI x3 IRQ x5 CKO /IRQ_MY x3 A[1:24] LCDDON
/WAIT D[0:15]
CPU Bus
C B
LCD module
CN402
with
(20P)
LVDS Tx
Touch Panel
IC401 (48P)
+3.3L
CN151 (6P)
LCDC
+24D
+5D
DC-DC
CN101 IC150
(8P)
(6P)
IC106
+12D
IC101
(24P)
+5D
(64P)
15 LED(BL)
Driver
CPU
M38039
+5D
PORT PORT
Touch Panel
SCI AD
Position Detect
PORT
(Tr. x5, AND x2)
CERALOCK
16MHz
X101
DCMS
/SYSRES E-Bus CN102
(6P)
See Page 10
CN151 (4P)
CPU, LCDC, USB, 10.4" LCD
■ BLOCK DIAGRAM 003 (CL3/CL1)
A
CL3/CL1
1
2
3
CN103 (4P)
CN150
+24D
(4P)
CN102
+12D
(5P)
4
CN401(5P)
CN085
(4P)
5
6
5