CL3/CL1
DSP6 のテス ト項目と実行中の表示 (右の Window 内)
1 : CPU Interface (Busy) .................................................. OK
2: CPU Interface (Data Bus) .......................................... OK
3: CPU Interface (Chip Select, TXB) ........................... OK
4: CPU Interface (Address Bus) .................................... OK
5: CPU Interface (BUS W/R Reg.) ............................... OK
6: DRAM Interface (Data Bus) . ...................................... OK
7: DRAM Interface (Address Bus) . ................................ OK
8: DRAM Interface (Address Bus & MPR) . .................. OK
9: SIO Connection...OK .........DSP6 → DSP6 の SIO test
10: PIO Connection...OK .........DSP6 → DSP6 の PIO test
DSP7 のテス ト項目と実行中の表示 (右の Window 内)
1 : CPU Interface (Data Bus) .......................................... OK
2: CPU Interface (Chip Select) . ..................................... OK
3: CPU Interface (Address Bus) .................................... OK
4: E-RAM Interface (Data Bus) . ..................................... OK
5: E-RAM Interface (Address Bus) . ............................... OK
6: SIO Connection (DSP7 → DSP6) ............................ OK
7: SIO Connection (DSP6 → DSP7) . ........................... OK
8: SIO Connection (DSP7 → DSP7) ............................ OK
9: DSP7 LSI Check (DSP7 ACC) . ................................ OK
DSP6、DSP7 共通、NG の場合の表示説明
1) CPU Interface/DRAM, E-RAM Interface
NG: ICxxx (1) 0000 0000 XXXX 0000 0000 0000 0000 X00X
MSB
IC 番号 DSP 番号 X =不良のビッ ト
2) SIO Connection (DSP7 → DSP6)...
NG: 1 ICxxx (1) [SOxx] → ICxxx (1) [SIxx]
156
1-8. SHARC Test
内容 CPU SHARC 間の通信チェック。
SHARC SDRAM チ ェ ッ ク (Address Bus、Data
Bus) 。
CPU と SHARC 間の FLAG ラインのチェック。
実行画面例
LSB