Isr Host Flag 2 (Hf2) Bit 3; Isr Host Flag 3 (Hf3) Bit 4; Isr (Reserved Status) Bit 5; Isr Dma Status (Dma) Bit 6 - Motorola DSP56156 Manual

INTERRUPT VECTOR REGISTER (IVR)

TRDY = TXDE ^ HRDF
The DSP reset will set TRDY.

5.11.4 ISR Host Flag 2 (HF2) Bit 3

The Host Flag 2 (HF2) bit indicates the state of Host Flag 2 (HF2) in the Host Control Reg-
ister (HCR). HF2 can only be changed by the DSP. HF2 is cleared by a DSP reset.

5.11.5 ISR Host Flag 3 (HF3) Bit 4

The Host Flag 3 (HF3) bit indicates the state of Host Flag 3 (HF3) in the Host Control Reg-
ister HCR. HF3 can only be changed by the DSP. HF3 is cleared by a DSP reset.

5.11.6 ISR (Reserved Status) Bit 5

This status bit is reserved for future expansion and will read as zero during host processor
read operations. Reserved bits should be written as zero for future compatibility.

5.11.7 ISR DMA Status (DMA) Bit 6

The DMA status bit (DMA) indicates that the host processor has enabled the DMA
mode of the HI (HM1 or HM0 =1). When the DMA status bit is clear, it indicates that the
DMA mode is disabled by the Host Mode bits HM0 and HM1 in the Interrupt Control
Register ICR and no DMA operations are pending. When DMA is set, it indicates that
the DMA mode is enabled and the host processor should not use the active DMA chan-
nel (RXH:RXL or TXH:TXL depending on DMA direction) to avoid conflicts with the
DMA data transfers.

5.11.8 ISR Host Request (HREQ) Bit 7

The Host Request (HREQ) bit indicates the status of the external Host Request HREQ
output pin. When the HREQ status bit is cleared, it indicates that the external HREQ pin
is deasserted and no host interrupts or DMA transfers are being requested. When the
HREQ status bit is set, it indicates that the external HREQ pin is asserted indicating that
the DSP is interrupting the host processor or that a DMA Transfer Request is being made.
The HREQ interrupt request may originate from one or more of 2 sources - the Receive
Byte Registers are full or the Transmit Byte Registers are empty. These conditions are
indicated by the Interrupt Status register (ISR) RXDF and TXDE status bits, respectively.
If the interrupt source has been enabled by the associated request enable bit in the Inter-
rupt Control Register ICR, HREQ will be set if one or more of the 2 enabled interrupt
sources is set. DSP reset will clear HREQ.
5.12

INTERRUPT VECTOR REGISTER (IVR)

The Interrupt Vector Register (IVR) is an 8-bit read/write register which contains the ex-
ception vector number for use with MC68000 processor family vectored interrupts. This
MOTOROLA HOST INTERFACE 5 - 17