Motorola DSP56156 Manual page 287

PERIPHERAL ADDRESSES
$FFFF Reserved for on-chip emulation
$FFFE
$FFFD TSMB1 SSI1 Register
$FFFC TSMA1 SSI1 Register
$FFFB RSMB1 SSI1 Register
$FFFA RSMA1 SSI1 Register
$FFF9 TX/RX SSI1 TX/RX Registers
$FFF8 SR/TSR SSI1 Status Register
$FFF7
$FFF6
$FFF5 TSMB0 SSI0 Register
$FFF4 TSMA0 SSI0 Register
$FFF3 RSMB0 SSI0 Register
$FFF2 RSMA0 SSI0 Register
$FFF1 TX/RX SSI0 TX/RX Registers
$FFF0 SR/TSR SSI0 Status Register
$FFEF Timer Preload Register(TPR)
$FFEE Timer Compare Register(TCPR)
$FFED Timer Count Register(TCTR)
$FFEC Timer Control Register(TCR)
$FFEB
$FFEA
$FFE9
$FFE8
$FFE7
$FFE6
$FFE5 HTX/HRX: Host TX/RX Register
$FFE4 HSR: Host Status Register
$FFE3 Port C Data Register (PCD)
$FFE2 Port B Data Register (PBD)
$FFE1
$FFE0
MOTOROLA
DSP56156 On-chip Peripheral Memory Map
CRX/CTX
COSR
Figure C-1 On-chip Peripherals
PROGRAMMING SHEETS
$FFDF IPR: Interrupt Priority Register
$FFDE BCR: Bus Control Register
$FFDD reserved for future use
$FFDC PLCR
$FFDB
$FFDA
$FFD9 CRB-SSI1 Control Register B
$FFD8 CRA-SSI1 Control Register A
$FFD7
$FFD6
$FFD5
$FFD4
$FFD3
$FFD2
$FFD1 CRB-SSI0 Control Register B
$FFD0 CRA-SSI0 Control Register A
$FFCF
$FFCE
$FFCD
$FFCC
$FFCB
$FFCA
$FFC9 reserved for test
$FFC8 COCR
$FFC7
$FFC6
$FFC5
$FFC4 HCR: Host Control Register
$FFC3 Port C Data Direction Register
$FFC2 Port B Data Direction Register
$FFC1 Port C Control Register (PCC)
$FFC0 Port B Control Register (PBC)
C - 3