Motorola DSP56156 Manual page 15

Figure
Number
6-32 Overall Response of the D/A Section
When Using the IIR Filter of Figure 6-31 . . . . . . . . . . . . . . . . . . . 6-53
6-33 Example 4 functional block diagram . . . . . . . . . . . . . . . . . . . . . 6-54
6-34 Example of Transmit and Receive Filter Performance Constraints . . . . . 6-55
6-35 Example of a Transmit Antialiasing-decimation IIR Filter . . . . . . . . . . 6-56
6-36 Overall Response of the A/D Section
when Using the IIR Filter of Figure 6-35 . . . . . . . . . . . . . . . . . . . 6-58
6-37 Example of a Receive Reconstruction-interpolation IIR Filter . . . . . . . . 6-59
6-38 Overall Response of the D/A Section
When Using the IIR Filter of Figure 6-37 . . . . . . . . . . . . . . . . . . . 6-61
6-39 Flowchart of a Decimation/Interpolation Routine
7-1 16-bit Timer General Block Diagram . . . . . . . . . . . . . . . . . . . . . 7-4
7-2 Timer Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7-3 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7-4 Standard Timer Operation with Overflow Interrupt . . . . . . . . . . . . . . 7-9
7-5 Standard Timer Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7-6
Write to the Count Register
After Writing to the Preload Register when the Timer is Disabled . . . . . . 7-10
7-7 Timer Disable After a Write to the Count Register . . . . . . . . . . . . . . 7-10
7-8 Write to the Count Register when the Timer is Enabled . . . . . . . . . . . 7-11
7-9 Write to DC7-DC0 when the Timer is Enabled . . . . . . . . . . . . . . . . 7-12
7-10 Standard Timer Operation with Compare Interrupt . . . . . . . . . . . . . 7-13
8-1 SSIx Internal Clock, Synchronous Operation . . . . . . . . . . . . . . . . 8-5
8-2 SSIx External Clock, Synchronous Operation . . . . . . . . . . . . . . . . 8-5
8-3 SSIx Internal Clock, Asynchronous Operation . . . . . . . . . . . . . . . . 8-5
8-4 SSIx External Clock, Asynchronous Operation . . . . . . . . . . . . . . . 8-5
8-5 SSIx Internal Clock, Synchronous Operation Dual Codec Interface . . . . . 8-6
8-6 SSI Clock Generator Functional Block Diagram . . . . . . . . . . . . . . . 8-6
8-7 SSIx Frame Sync Generator Functional Block Diagram . . . . . . . . . . . 8-8
8-8 SSIx Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
8-9 SSI Control Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
9-1 Frequency Synthesis Block Diagram and Control Register . . . . . . . . . 9-5
9-2 Three On-chip Clock Synthesis Examples . . . . . . . . . . . . . . . . . . 9-6
9-3 On-chip Frequency Synthesizer Programming Model Summary . . . . . . 9-10
A
A-1 DSP56156 Bootstrap Program Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
MOTOROLA
List of Figures (Continued)
Title
SECTION 7
SECTION 8
SECTION 9
LIST of FIGURES
. . . . . . . . . . . . . . 6-67
Page
Number
xv