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Application:
SSI
SSI Control Register A (CRA)
SSI0 Address $FFD0 Read/Write
SSI1 Address $FFD8 Read/Write
Reset = $0000
Clock Source Direction
0 = External Clock
1 = Internal Clock
Clock Polarity
0 = ∏Data Out ↑, Data In ↓1 = ∏Data Out ↓, Data In ↑
MSB Position
0 = MSB First
1 = LSB First
Frame Sync Length
0 = ∏ Word Sync
1 = ∏ Bit Sync
Frame Sync Invert
0 = ∏ Active High
1 = ∏ Active Low
Sync/Async
0 = ∏ Async
1 = Sync
Mode Select
0 = ∏ Normal 1 = Network
Transmit Enable
0 = ∏ Disable 1 = Enable
Receive Enable
0 = ∏ Disable 1 = Enable
Transmit Interrupt Enable
0 = ∏ Disable 1 = Enable
Receive Interrupt Enable
0 = ∏ Disable 1 = Enable
SSI Control Register B (CRB)
SSI0 Address $FFD1 Read/Write
SSI1 Address $FFD9 Read/Write
Reset = $0000
MOTOROLA
DSP56156 SSI Programming Sheet
Word Length Control
00 = 8 Bits/Word
01 = 8 with Log Exp/Comp
10 = 12 Bits/Word
11 = 16 Bits/Word
Prescaler Range
0 = / 1
1 = / 8
15 14 13 12 11 10
PSR WL1 WL0 DC4
Figure C-39 SSI Control Register A (CRA)
15 14 13 12 11 10
RIE
TIE
RE
Figure C-40 SSI Control Register B (CRB)
PROGRAMMING SHEETS
Frame Rate Divider Control
00000 = 1
11111 = 32
9
8
7
DC3 DC2 DC1 DC0 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0
9
8
7
TE
MOD SYN
FSI
FSL SHFD SCKP SCKD FSD1 A/MU FSD0 OF1
Date:
Programmer:
Sheet 4 of 5
Prescale Modulus Select
6
5
4
3
2
Frame Sync Directions
SYN FSD0 FSD1 Mode
SC1x
0
0
0
Async RFS in TFS in
0
0
1
Async RFS out TFS out
0
1
0
Async RFS in TFS out
0
1
1
—
—
1
0
0
Sync
—
1
0
1
Sync
—
1
1
0
—
—
1
1
1
Sync
F1 out F0 out
A/Mu Law Selection
Iff WL1 = 0 and WL0 = 1
0 = A Law
1 = µ Law
Serial Output Flags
Enabled when SYN = 1
and FSDx = 1
6
5
4
3
2
C - 37
1
0
SC0x
—
FS in
FS out
—
1
0
OF0
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