Motorola DSP56156 Manual page 203

DSP56156
PC0/PC5
PC1/PC6
PC2/PC7
PC3/PC8–SC1x
PC4/PC9–SC0x
Figure 8-5 SSIx Internal Clock, Synchronous Operation Dual Codec Interface
Figure 8-6 shows the internal clock path connections in block diagram form. The serial bit
clock can be internal or external depending on SCKD bit in the control register.
Fosc
/2
SCK
Figure 8-6 SSI Clock Generator Functional Block Diagram
8 - 6 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1)
SSIx DATA AND CONTROL PINS
STDx
SRDx
SCKx
F1
F0
PSR PM0-PM7
Prescale Divider
/1 or /8 /1 to /256
SCKD (1= output)
Internal Bit Clock
RDD
TDD
CODEC
TDC/RDC
1
TDE/RDE
RDD
TDD
CODEC
TDC/RDC
0
TDE/RDE
/2
WL1, WL0 Control Reset
Word
Length Divider
RX Shift
Register
TX Shift
Register
Word Clock
Rx Data
Tx Data
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