Motorola DSP56156 Manual page 257

internal clock phase that is generated by the VCO down counter. At the point where there
is negligible phase difference and the frequency of the two inputs is identical, the PLL is
in the "locked" state.
The filter receives signals from the phase comparator, and either increases or decreases
the voltage fed to the Voltage Controlled Oscillator (VCO). An external capacitor is con-
nected to the SXFC pin (described in Section 2.5) and determines the PLL operating char-
acteristics.
When the PLL is in the stage where it is acquiring the proper phase and frequency, it op-
erates in a wide bandwidth mode. After the PLL locks on to the proper phase/frequency,
it reverts to the narrow bandwidth mode, which is useful for tracking small changes in the
EXTAL clock due to frequency drift.
9.1.1.2 Voltage Controlled Oscillator (VCO)
The VCO is controlled by the phase difference between the two inputs to the phase com-
parator. The VCO output is divided by four and then by the 4-bit VCO count down
counter (see Figure 9-1) which lowers the frequency fed to the phase comparator. This
forms a negative feedback loop that requires that the VCO run at a faster rate than the
reference input to the phase comparator. The net effect is that the down counter
becomes a frequency multiplier.
9.1.1.3 Dividers
The four divider bits, ED3-ED0, define the on-chip PLL resolution. The four down counter
bits, YD3-YD0, control the down counting in the PLL feedback loop causing it to divide by
the value YD+1. The DSP core system frequency is controlled (first divided by the con-
tents in ED and then multiplied by the contents of YD) by the PLL Control Register
(PLCR) frequency control bits as follows:
where ED is the value contained in ED3-ED0,YD the value contained in YD3-YD0, and
Fext is the clock frequency applied to the EXTAL pin.
Note: The STOP instruction does not power down the PLL if the PLL is enabled
(PLLD=0) when entering the STOP mode. STOP will power down the ED register
and the CLKO circuitry if the PLL is disabled (PLLD=1) and if the CLKO is turned
off (CD=0 in OMR) when entering the STOP mode (see section 9.3.5).
9 - 4
INTRODUCTION
÷ (ED +1)] x 4[YD+1]
F = [F
osc ext
ON-CHIP FREQUENCY SYNTHESIZER MOTOROLA