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7.6.4
TCR Compare Interrupt Enable (CIE) Bit 10
When the Compare Interrupt Enable bit (CIE) is set, the DSP will be interrupted at the next
event after the count register reaches the value contained in the compare register. When
the CIE bit is cleared, this interrupt in disabled. CIE bit is cleared on hardware RESET and
software reset (RESET instruction).
7.6.5
TCR Timer Output Enable (TO2-TO0) Bit 11-13
The three timer output enable bits (TO2-TO0) are used to program the function of the tim-
er output pin (TOUT). Table 7-1 shows the relationship between the value of TO2-TO0
and the function of the TOUT pin. These bits are cleared on hardware RESET and soft-
ware reset (RESET instruction).
TO2 TO1 TO0
0
0
0
0
0
1
Compare/Overflow pulse
0
1
0
0
1
1
1
0
0
Overflow/Compare toggle
1
0
1
Compare/Overflow toggle
1
1
0
1
1
1
Note: If one of the toggle modes is selected and TE is written as zero while the TOUT pin is either high
or low, the pin remains in the same state. If the TO2 bit is written as zero with the TE bit, the pin will
remain high and will go low when the timer is re-enabled. Writing the TO2 bit as zero before writing
the TE bit as zero will clear the TOUT pin, i.e., in the non-toggle modes, TOUT is normally low.
7.6.6
TCR Inverter Bit (INV) Bit 14
When the inverter bit INV is set, the external signal coming in the TIN pin is inverted before
entering the 8-bit decrement register. All 1 to 0 transitions of the TIN pin will then decre-
ment the decrement register. When the INV is cleared, the external signal on TIN is not
MOTOROLA
TIMER CONTROL REGISTER (TCR)
Table 7-1 TOUT Pin Function
Function of TOUT
TOUT disabled
Overflow pulse
Compare pulse
Overflow toggle
Compare toggle
16-BIT TIMER AND EVENT COUNTER
Signal on TOUT
Icyc/2
7 - 7
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