Crb A/Mu Law Selection Bit (A/Mu) Bit 3; Transmit And Receive Frame Sync Directions - (Fsd1) Bit 4; Crb Clock Source Direction (Sckd) Bit 5; Crb Clock Polarity Bit (Sckp) Bit 6 - Motorola DSP56156 Manual

8.12.3

CRB A/Mu Law Selection Bit (A/MU) Bit 3

When WL1-WL0 control bit of CRA are programmed for 8-bit exchange with logarithmic
expansion/compression, the bit A/MU selects which law is used by the expanding/com-
panding hardware. This bit is a don't care bit otherwise.
If A/Mu=0, the A law is selected and if A/MU=1, the µ law is selected. Companding/Ex-
panding hardware follows CCITT recommendation G.711.
8.12.4

Transmit and Receive Frame Sync Directions - (FSD1) Bit 4

See Paragraph 8.12.2.
8.12.5

CRB Clock Source Direction (SCKD) Bit 5

The Clock Source Direction bit selects the source of the clock signal used to clock the
Transmit Shift Register and the Receive Shift Register. When SCKD is set, the clock
source is internal and is the bit clock output of the SSI clock generator. This clock appears
at the SCK pin (SCKD=1). When SCKD is cleared, the clock source is external; the inter-
nal clock generator is disconnected from the SCK pin and an external clock source may
drive this pin to clock the Transmit Shift Register and the Receive Shift Register in either
mode.
8.12.6

CRB Clock Polarity Bit (SCKP) Bit 6

The clock polarity bit controls on which bit clock edge data is clocked out and latched in.
If SCKP= 0, the data is clocked out on the rising edge of the bit clock and received in on
the falling edge of the clock. If SCKP = 1, the falling edge of the clock is used to clock the
data out and the rising edge of the clock is used to latch the data in.
8.12.7

CRB MSB Position Bit (SHFD) Bit 7

The SHFD bit controls whether MSB or LSB is transmitted and received first. If SHFD = 0,
the data is exchanged MSB first; if SHFD = 1, the LSB is exchanged first.
8.12.8

CRB Frame Sync Length (FSL) Bit 8

The Frame Sync Length bit selects the type of frame sync to be generated or recognized.
If FSL=1, the frame sync will be one bit-clock long during the bit period immediately pre-
ceding the first bit period of the word being transferred. If FSL=0, the frame sync will be
one data word in length.
8.12.9

CRB Frame Sync Invert (FSI) Bit 9

The Frame Sync Invert (FSI) bit selects the logic of frame sync I/O and I/O flag pins. If
FSI=1, the frame sync or flag pins are active low. If FSI=0, the frame sync or flag pins are
active high.
MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1)
SSI CONTROL REGISTER B (CRB)
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