Instruction Set Summary; Instruction Groups - Motorola DSP56156 Manual

When the Clock out Disable bit (CD) is cleared in the OMR, a clock out signal comes out
of the CLKO pin. Setting the CD bit will disable the signal coming out of the CLKO pin one
instruction cycle after the bit has been set.
Note: When a bit of the OMR is changed by an instruction, a delay of one instruction cycle
is necessary before the new mode comes into effect.
1.7

INSTRUCTION SET SUMMARY

As indicated by the programming model, the DSP architecture can be viewed as three
functional units operating in parallel (Data ALU, AGU, and PCU). The goal of the instruc-
tion set is to keep each of these units busy each instruction cycle. This achieves maximum
speed and minimum use of program memory.
This section introduces the DSP instruction set and instruction format. The complete
range of instruction capabilities combined with the flexible addressing modes provide a
very powerful assembly language for digital signal processing algorithms. The instruction
set has also been designed to allow efficient coding for future high-level DSP language
compilers. Execution time is enhanced by the hardware looping capabilities.
1.7.1

Instruction Groups

The instruction set is divided into the following groups:
- Arithmetic
- Logical
- Bit Field Manipulation
- Loop
- Move
- Program Control
MOTOROLA

INSTRUCTION SET SUMMARY

Table 1-10
Actions of the Saturation Mode (SA=1)
exp[7] exp[0] msp[15]
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
DSP56156 OVERVIEW
result in accumulator
unchanged
$00 7FFF FFFF
$00 7FFF FFFF
$00 7FFF FFFF
$FF 8000 0000
$FF 8000 0000
$FF 8000 0000
unchanged
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