Timer; Host Interface (Hi) - Motorola DSP56156 Manual

codecs, other DSPs, microprocessors, and peripherals. Selectable logarithmic compres-
sion and expansion (µ-law and A-law) is available for easier interface with PCM monocir-
cuits and PCM highways. The SSIx interface consists of independent transmitter and
receiver sections and a common SSI clock generator. Each of the following characteris-
tics of the SSI can be independently defined: the number of bits per word, the protocol or
mode, the clock, and the transmit/receive synchronization. Three modes of operation are
available: Normal, Network, and On-Demand. The Normal Mode is typically used to inter-
face with devices on a regular or periodic basis. In this mode the SSI functions with one
data word of I/O per frame. The Network Mode provides time slots in addition to a bit clock
and a frame synchronization pulse. The SSI functions with from 2 to 32 words of I/O per
frame in the Network Mode. This mode is typically used in star or ring Time Division Mul-
tiplex (TDM) networks with other DSP56156s and/or codecs. The On-Demand Mode is a
data driven mode and is a special case of the Network Mode. There are no time slots de-
fined. This mode is intended to be used to interface to devices on a non-periodic basis.
Since the transmitter and receiver sections of the SSI are independent, they may be pro-
grammed to be synchronous (use a common clock and frame sync) or asynchronous (use
a common clock but different frame sync) with respect to each other. The SSI supports a
subset of the Motorola SPI interface. The SSI requires three to six pins depending on the
operating mode selected.
1.4.4

Timer

The Timer is a general purpose 16-bit timer/event counter with internal or external clock-
ing which can be used to interrupt the DSP or to signal an external device at periodic in-
tervals, after counting internal events or after counting external events. A Timer Input pin
(TIN) can be used as an event counter input and a Timer Output pin (TOUT) can be used
for timer pulse or timer clock generation.
The timer includes three 16-bit registers: the Timer Count Register (TCTR), the Timer Pre-
load Register (TPR), and the Timer Compare Register (TCPR). An additional Timer Con-
trol Register (TCR) controls the timer operations.
A decrement register, programmed by the control register, is not available to the user. All
other registers are memory mapped read/write registers.
1.4.5

Host Interface (HI)

The HI is a byte-wide parallel slave port which may be connected directly to the data bus
of a host processor. The host processor may be any of a number of popular microcom-
puters or microprocessors, another DSP, or DMA hardware. The DSP56156 has an 8-bit
bidirectional data bus and 7 control lines to control data transfers. The HI appears as a
memory mapped peripheral, occupying 8 bytes in the host processor's address space and
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EXTERNAL BUS, I/O, AND ON-CHIP PERIPHERALS
DSP56156 OVERVIEW MOTOROLA