Motorola DSP56156 Manual page 259

13 MHz
13 MHz
EXTAL
9.72 MHz
EXTAL
16.8 MHz
EXTAL
Figure 9-2 Three On-chip Clock Synthesis Examples
9.2.2 Example Two
In the second example, the 4-bit input divider divides the input clock by 5 providing a 1.944
MHz clock to the Σ∆ codec and to the PLL. The PLL can multiply the 1.944 MHz clock up
9 - 6
ON-CHIP CLOCK SYNTHESIS EXAMPLES
GSM=1
÷ 6.5
4-bit input divider
PHASE
÷ 1 to ÷ 16
ED3-ED0
GSM=0
÷ 6.5
4-bit input divider
÷ 5 PHASE
COMP.
ED3-ED0=4
GSM=0
÷ 6.5
4-bit input divider
÷ 10 PHASE
COMP.
ED3-ED0=9
ON-CHIP FREQUENCY SYNTHESIZER
2 MHz
CODEC
Filter
COMP.
4-bit VCO down counter
÷ 1 to ÷ 16
YD3-YD0
1.944 MHz
CODEC
Filter
4-bit VCO down counter
÷ 1 to ÷ 16
YD3-YD0
1.68 MHz
CODEC
Filter
4-bit VCO down counter
÷ 1 to ÷ 16
YD3-YD0
PLLE=1
Fosc
VCO
PLLE=0
÷4
PLLE=1
Fosc
VCO
PLLE=0
÷4
PLLE=1
Fosc
VCO
PLLE=0
÷4
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