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S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X
BLOCK DIAGRAM
TAOUT/P0.4
8-Bit Timer/
T1CLK/P0.3
Counter A
8-Bit Timer/
TBOUT/P0.5
Counter B
P0.0/INT0
P0.1/INT1
P0.2/INT2
P0.3/T1CLK
P0.4/TAOUT
P0.5/TBOUT
P0.6/CLKOUT
P0.7/BUZ
P1.0/SCK
P1.1/SO
P1.2/SI
P1.3/INT3
P1.4/INT4
P1.5/INT5
P1.6/INT6
P1.7/INT7
P2.0/SEG31/V
BLDREF
P2.1-P2.7/SEG30-SEG24
P3.0-P3.7/SEG23-SEG16
P4.0-P4.7/SEG15-SEG8
nRESET
16-Bit
Timer/
Counter 1
Port I/O and Interrupt Control
I/O Port 0
SAM88RC CPU
I/O Port 1
544/288 Byte
Register File
I/O Port 2
I/O Port 3
I/O Port 4
Figure 1-1. Block Diagram
X
X
IN
OUT
V
REG
XT
XT
IN
OUT
16/8/4-Kbyte
ROM
PRODUCT OVERVIEW
Watchdog
Timer
Basic Timer
Low Voltage
Reset
Clock Out
CLKOUT/P0.6
Block
Battery Level
V
/
BLDREF
Detector
P2.0/SEG31
Watch Timer
BUZ/P0.7
COM0-COM3/P6.0-P6.3
SEG0-SEG7/P5.7-P5.0
SEG8-SEG15/P4.7-P4.0
LCD
SEG16-SEG23/P3.7-P3.0
Driver
SEG24-SEG30/P2.7-P2.1
SEG31/P2.0/V
VLC0-VLC2
P1.0/SCK
SIO
P1.1/SO
P1.2/SI
P6.0-P6.3/
I/O Port 6
COM0-COM3
P5.0-P5.7/
I/O Port 5
SEG7-SEG0
BLDREF
1-3
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