Peripheral Interrupt Control Registers; Interrupt Source Control And Data Registers - Samsung S3C8275X User Manual

INTERRUPT STRUCTURE

PERIPHERAL INTERRUPT CONTROL REGISTERS

For each interrupt source there is one or more corresponding peripheral control registers that let you control the
interrupt generated by the related peripheral (see Table 5-3).
Interrupt Source
Timer B match
Timer 1/A match
SIO interrupt
Watch timer overflow
P0.0 external interrupt
P0.1 external interrupt
P0.2 external interrupt
P1.3 external interrupt
P1.7 external interrupt
P1.6 external interrupt
P1.5 external interrupt
P1.4 external interrupt
NOTE: If an interrupt is un-mask (Enable interrupt level) in the IMR register, the pending bit and enable bit of the interrupt
should be written after a DI instruction is executed.
5-8
Table 5-3. Interrupt Source Control and Data Registers
Interrupt Level
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X
Register(s)
TBCON, TBDATA, TBCNT
TACON, TADATA, TACNT
SIOCON
SIODATA
SIOPS
WTCON
P0CONL
EXTICONL
EXTIPND
P0CONL
EXTICONL
EXTIPND
P0CONL
EXTICONL
EXTIPND
P1CONL
EXTICONL
EXTIPND
P1CONH
EXTICONH
EXTIPND
Location(s) in Set 1
E7H, E5H, E3H, bank 1
E6H, E4H, E2H, bank 1
E1H, bank 0
E2H, bank 0
E3H, bank 0
E1H, bank 1
E5H, bank 0
F9H, bank 0
F7H, bank 0
E5H, bank 0
F9H, bank 0
F7H, bank 0
E5H, bank 0
F9H, bank 0
F7H, bank 0
E8H, bank 0
F9H, bank 0
F7H, bank 0
E7H, bank 0
F8H, bank 0
F7H, bank 0