Sub Subtract - Samsung S3C8275X User Manual

INSTRUCTION SET
SUB
— Subtract
SUB dst,src
dst ← dst – src
Operation:
The source operand is subtracted from the destination operand and the result is stored in the
destination. The contents of the source are unaffected. Subtraction is performed by adding the
two's complement of the source operand to the destination operand.
Flags: C: Set if a "borrow" occurred; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the
sign of the result is of the same as the sign of the source operand; cleared otherwise.
D: Always set to "1".
H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result;
set otherwise indicating a "borrow".
Format:
opc
opc
opc
Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H
= 0AH:
SUB
SUB
SUB
SUB
SUB
SUB
In the first example, if working register R1 contains the value 12H and if register R2 contains the
value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination
value (12H) and stores the result (0FH) in destination register R1.
6-82
dst | src
src dst
dst src
→
R1,R2 R1 = 0FH, R2 = 03H
→
R1,@R2 R1 = 08H, R2 = 03H
→
01H,02H Register 01H = 1EH, register 02H = 03H
01H,@02H →
Register 01H = 17H, register 02H = 03H
→
01H,#90H Register 01H = 91H; C, S, and V = "1"
→
01H,#65H Register 01H = 0BCH; C and S = "1", V = "0"
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X
Bytes Cycles Opcode
2 4
6
3 6
6
3 6
Addr Mode
(Hex) dst src
22 r r
23 r lr
24 R R
25 R IR
26 R IM