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S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X
8
RESET and POWER-DOWN
SYSTEM RESET
OVERVIEW
During a power-on reset, the voltage at V
nRESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock. This
procedure brings the S3C8275X/C8278X/C8274X into a known operating status.
To allow time for internal CPU clock oscillation to stabilize, the nRESET pin must be held to Low level for a
minimum time interval after the power supply comes within tolerance. The minimum required time of a reset
operation for oscillation stabilization is 1 millisecond.
Whenever a reset occurs during normal operation (that is, when both V
nRESET pin is forced Low level and the reset operation starts. All system and peripheral control registers are
then reset to their default hardware values
In summary, the following sequence of events occurs during a reset operation:
•
All interrupt is disabled.
•
The watchdog function (basic timer) is enabled.
•
Ports 0-6 are set to input mode, and all pull-up resistors are disabled for the I/O port.
•
Peripheral control and data register settings are disabled and reset to their default hardware values.
•
The program counter (PC) is loaded with the program reset address in the ROM, 0100H.
•
When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM
location 0100H (and 0101H) is fetched and executed at normal mode by smart option.
•
The reset address of ROM can be changed by a smart option only in the S3F8275X (Full-Flash Device).
Refer to the chapter 16. Embedded Flash Memory Interface for more detail contents.
NORMAL MODE RESET OPERATION
In normal (masked ROM) mode, the Test pin is tied to V
ROM (The external interface is not automatically configured).
To program the duration of the oscillation stabilization interval, you make the appropriate settings to the
basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic
timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can
disable it by writing "1010B" to the upper nibble of BTCON.
goes to High level and the nRESET pin is forced to Low level. The
DD
. A reset enables access to the 16/8/4-Kbyte on-chip
SS
NOTE
RESET
and nRESET are High level), the
DD
and POWER-DOWN
8-1
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