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S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X
Vector Address
Decimal
Value
Value
256
100H
242
240
244
246
224
226
228
230
238
236
234
232
NOTES:
1.
Interrupt priorities are identified in inverse order: "0" is the highest priority, "1" is the next highest, and so on.
2.
If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority
over one with a higher vector address. The priorities within a given level are fixed in hardware.
Table 5-1. Interrupt Vectors
Interrupt Source
Hex
Basic timer overflow
F2H
Timer B match
F0H
Timer 1/A match
F4H
SIO interrupt
F6H
Watch timer overflow
E0H
P0.0 external interrupt
E2H
P0.1 external interrupt
E4H
P0.2 external interrupt
E6H
P1.3 external interrupt
EEH
P1.7 external interrupt
ECH
P1.6 external interrupt
EAH
P1.5 external interrupt
E8H
P1.4 external interrupt
INTERRUPT STRUCTURE
Request
Interrupt
Priority in
Level
Level
−
Reset
IRQ0
1
0
−
IRQ1
−
IRQ2
−
IRQ3
−
IRQ4
−
IRQ5
−
IRQ6
IRQ7
3
2
1
0
Reset/Clear
H/W
S/W
√
√
√
√
√
√
√
√
√
√
√
√
√
5-5
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