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ANDI
to SR
Operation:
Assembler
Syntax:
Attributes:
Description:
tents of the status register and stores the result in the status register. All implemented
bits of the status register are affected.
Condition Codes:
X
N
Z
*
*
*
X
Cleared if bit 4 of immediate operand is zero. Unchanged otherwise.
N
Cleared if bit 3 of immediate operand is zero. Unchanged otherwise.
Z
Cleared if bit 2 of immediate operand is zero. Unchanged otherwise.
V
Cleared if bit 1 of immediate operand is zero. Unchanged otherwise.
C
Cleared if bit 0 of immediate operand is zero. Unchanged otherwise.
Instruction Format:
15
14
13
0
0
0
CPU32
REFERENCE MANUAL
AND Immediate to the Status Register
(Privileged Instruction)
If supervisor state
then Source • SR →SR
else TRAP
ANDI #〈data〉, SR
Size = (Word)
Performs an AND operation of the immediate operand with the con-
V
C
*
*
12
11
10
9
0
0
0
1
INSTRUCTION SET
8
7
6
5
0
0
1
1
WORD DATA
ANDI
to SR
4
3
2
1
1
1
1
0
MOTOROLA
0
0
4-31
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