Virtual Memory; Loop Mode Instruction Execution - Motorola CPU32 Reference Manual

• Instruction Set Enhancements
— High-Precision Multiply and Divide
— Trap On Condition Codes
— Upper and Lower Bounds Checking
• Enhanced Breakpoint Instruction
• Trace on Change of Flow
• Table Lookup and Interpolate Instruction
• Low-Power Stop Instruction
• Hardware Breakpoint Signal, Background Mode
• 16.77-MHz Operating Frequency (–40 to 125°C)
• Fully Static Implementation

1.1.1 Virtual Memory

A system that supports virtual memory has a limited amount of high-speed physical
memory that can be accessed directly by the processor and maintains an image of a
much larger "virtual" memory on a secondary storage device. When the processor at-
tempts to access a location in the virtual memory map that is not resident in physical
memory, a page fault occurs. The access to that location is temporarily suspended
while the necessary data is fetched from secondary storage and placed in physical
memory. The suspended access is then restarted or continued. The CPU32 uses in-
struction restart, which requires that only a small portion of the internal machine state
be saved. After correcting the fault, the machine state is restored, and the instruction
is refetched and restarted. This process is completely transparent to the application
program.

1.1.2 Loop Mode Instruction Execution

The CPU32 has several features that provide efficient execution of program loops.
One of these features is the DBcc looping primitive. To increase the performance of
the CPU32, a loop mode has been added to the processor. The loop mode is used by
any single-word instruction that does not change the program flow. Loop mode is im-
plemented in conjunction with the DBcc instruction. Figure 1-1 shows the required
form of an instruction loop for the processor to enter loop mode.
Loop mode is entered when DBcc is executed and loop displacement is –4. Once in
loop mode, the processor performs only data cycles associated with the instruction
and suppresses instruction fetches. Termination condition and count are checked after
each execution of looped instruction data operations. The CPU automatically exits
loop mode for interrupts or other exceptions.
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