Table of Contents
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Paragraph
1.1
Features .................................................................................................... 1-1
1.1.1
Virtual Memory ..................................................................................1-2
1.1.2
Loop Mode Instruction Execution ......................................................1-2
1.1.3
Vector Base Register ........................................................................ 1-3
1.1.4
Exception Handling ........................................................................... 1-3
1.1.5
Enhanced Addressing Modes ........................................................... 1-4
1.1.6
Instruction Set ...................................................................................1-4
1.1.6.1
Table Lookup and Interpolation Instructions ............................. 1-4
1.1.6.2
Low-Power Stop Instruction ......................................................1-6
1.1.7
Processing States ............................................................................. 1-6
1.1.8
Privilege States ................................................................................. 1-6
1.2
Block Diagram ...........................................................................................1-6
2.1
Programming Model ..................................................................................2-1
2.2
Registers ................................................................................................... 2-2
2.3
Data Types ................................................................................................ 2-3
2.3.1
Organization in Registers .................................................................. 2-4
2.3.1.1
Data Registers .......................................................................... 2-4
2.3.1.2
Address Registers ..................................................................... 2-5
2.3.1.3
Control Registers ...................................................................... 2-5
2.3.2
Organization in Memory .................................................................... 2-6
3.1
Program and Data References .................................................................. 3-1
3.2
Notation Conventions ................................................................................ 3-2
3.3
Implicit Reference ...................................................................................... 3-2
3.4
Effective Address ...................................................................................... 3-3
3.4.1
Register Direct Mode .........................................................................3-3
3.4.1.1
Data Register Direct .................................................................. 3-3
3.4.1.2
Address Register Direct ............................................................ 3-3
3.4.2
Memory Addressing Modes ...............................................................3-4
3.4.2.1
Address Register Indirect .......................................................... 3-4
CPU32
REFERENCE MANUAL
TABLE OF CONTENTS
Title
PREFACE
SECTION 1
OVERVIEW
SECTION 2
SECTION 3
Page
MOTOROLA
iii
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