Organization In Registers; Data Registers - Motorola CPU32 Reference Manual

2.3.1 Organization in Registers

The eight data registers can store data operands of 1, 8, 16, 32, and 64 bits and ad-
dresses of 16 or 32 bits. The seven address registers and the two stack pointers are
used for address operands of 16 or 32 bits. The PC is 32 bits wide.

2.3.1.1 Data Registers

Each data register is 32 bits wide. Byte operands occupy the low-order 8 bits, word
operands, the low-order 16 bits, and long-word operands, the entire 32 bits. When a
data register is used as either a source or destination operand, only the appropriate
low-order byte or word (in byte or word operations, respectively) is used or changed
— the remaining high-order portion is neither used nor changed. The least significant
bit (LSB) of a long-word integer is addressed as bit zero, and the most significant bit
(MSB) is addressed as bit 31. Figure 2-4 shows the organization of various types of
data in the data registers.
31 30
MSB
31
HIGH-ORDER BYTE
31
HIGH-ORDER WORD
31
63 62
MSB
31
Figure 2-4 Data Organization in Data Registers
Quad-word data consists of two long words: for example, the product of 32-bit multiply
or the quotient of 32-bit divide operations (signed and unsigned). Quad words may be
organized in any two data registers without restrictions on order or pairing. There are
no explicit instructions for the management of this data type; however, the MOVEM in-
struction can be used to move a quad word into or out of the registers.
MOTOROLA
2-4
24 23
MIDDLE HIGH BYTE
LONG WORD
LONG WORD
QUAD WORD
HIGH-ORDER LONG WORD
LOW-ORDER LONG WORD
ARCHITECTURE SUMMARY
BYTE
16 15
MIDDLE LOW BYTE
WORD
16 15
LOW-ORDER WORD
1 0
LSB
8 7
LOW-ORDER BYTE
1 0
LSB
CPU32
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