System Control Instructions - Motorola CPU32 Reference Manual

Instruction
Scc
BRA
BSR
JMP
JSR
NOP
RTD
RTR
RTS
To specify conditions for change in program control, condition codes must be substi-
tuted for the letters "cc" in conditional program control opcodes. Condition test mne-
monics are given below. Refer to 4.3.10 Condition Tests for detailed information on
condition codes.
CC—Carry clear
CS—Carry set
EQ—Equal
F—False*
GE—Greater or equal
GT—Greater than
HI—High
LE—Less or equal
*Not applicable to the Bcc instruction

4.3.9 System Control Instructions

Privileged instructions, trapping instructions, and instructions that use or modify the
condition code register provide system control operations. All of these instructions
cause the processor to flush the instruction pipeline. Table 4-9 summarizes the in-
structions. The preceding list of condition tests also applies to the TRAPcc instruction.
Refer to 4.3.10 Condition Tests for detailed information on condition codes.
Instruction
ANDI
EORI
MOVE
CPU32
REFERENCE MANUAL
Table 4-8 Program Control Operations
Syntax Operand Size
〈ea〉
8
Unconditional
〈label〉
8, 16, 32
〈label〉
8, 16, 32
〈ea〉
none
〈ea〉
none
none none
Returns
#〈d〉 16
none none
none none
Table 4-9 System Control Operations
Syntax Size
Privileged
#〈data〉, SR 16
#〈data〉, SR 16
〈ea〉, SR
16
SR, 〈ea〉
16
INSTRUCTION SET
Operation
If condition true, then destination bits are set to one;
else, destination bits are cleared to zero
PC + d → PC
SP – 4 → SP; PC → (SP); PC + d → PC
Destination → PC
SP – 4 → SP; PC → (SP); destination → PC
PC + 2 → PC
(SP) → PC; SP + 4 + d → SP
(SP) → CCR; SP + 2 → SP; (SP) → PC;
SP + 4 → SP
(SP) → PC; SP + 4 → SP
LS—Low or same
LT—Less than
MI—Minus
NE—Not equal
PL—Plus
T—True
VC—Overflow clear
VS—Overflow set
Operation
Data • SR → SR
Data ⊕ SR → SR
Source → SR
SR → Destination
MOTOROLA
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