Motorola CPU32 Reference Manual page 325

Mnemonic
Bcc Supports 32-Bit Displacement
BFxxxx Bit Field Instructions (BFCHG, BFCLR, BFEXTS,
BFEXTU, BFFO, BFINS, BFSET, BFTST)
BGND Background Operation
BKPT New Instruction Function
BRA Supports 32-Bit Displacement
BSR Supports 32-Bit Displacement
CALLM New Instruction
CAS,CAS2 New Instruction
CHK Supports 32-Bit Operands
CHK2 New Instruction
CMP1 Supports Program Counter Relative Addressing
CMP2 New Instruction
cp Coprocessor Instructions
DIVS/DIVU Supports 32-Bit and 64-Bit Operations
EXTB Supports 8-Bit Extend to 32 Bits
LINK Supports 32-Bit Displacement
LPSTOP New Instruction
MOVEC Supports New Control Registers
MULS/MULU Supports 32-Bit Operands and 64-Bit Results
PACK New Instruction
RTM New Instruction
TBLSN,TBLUN New Instruction
TBLS,TBLU
TST Supports Program Counter Relative, Immediate, and
An Addressing
TRAPcc New Instruction
UNPK New Instruction
CPU32
REFERENCE MANUAL
Table A-1 M68000 instruction Set Extensions
Description
M68000 FAMILY SUMMARY
CPU32 M68020
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MOTOROLA
A-3