Command Sequence Diagram - Motorola CPU32 Reference Manual

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Operand Size:
For sized operations, this field specifies the operand data size. All addresses are
expressed as 32-bit absolute values. The size field is encoded as follows:
Address/Data (A/D) Field:
The A/D field is used by commands that operate on address and data registers. It
determines whether the register field specifies a data or address register. One in-
dicates an address register; zero, a data register. For other commands, this field
may be interpreted differently.
Register Field:
In most commands, this field specifies the register number when operating on an
address or data register.
Extension Words (as required):
At this time, no command requires an extension word to specify fully the operation
to be performed, but some commands require extension words for addresses or
immediate data. Addresses require two extension words because only absolute
long addressing is permitted. Immediate data can be either one or two words in
length — byte and word data each require a single extension word, long-word data
requires two words. Both operands and addresses are transferred most significant
word first.

7.2.8.2 Command Sequence Diagram

A command sequence diagram illustrates the serial bus traffic for each command.
Each bubble in the diagram represents a single 17-bit transfer across the bus. The top
half in each diagram corresponds to the data transmitted by the development system
to the CPU; the bottom half corresponds to the data returned by the CPU in response
to the development system commands. Command and result transactions are over-
lapped to minimize latency.
Figure 7-10 demonstrates the use of command sequence diagrams.
The cycle in which the command is issued contains the development system com-
mand mnemonic (in this example, read memory location). During the same cycle, the
CPU responds with either the lowest order results of the previous command or with a
command complete status (if no results were required).
During the second cycle, the development system supplies the high-order 16 bits of
the memory address. The CPU returns a "not ready" response unless the received
command was decoded as unimplemented, in which case the response data is the il-
legal command encoding. If an illegal command response occurs, the development
system should retransmit the command.
MOTOROLA
7-12
Encoding
00
01
10
11
DEVELOPMENT SUPPORT
Operand Size
Byte
Word
Long
Reserved
REFERENCE MANUAL
CPU32

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