Prefetch Controller - Motorola CPU32 Reference Manual

The bus controller and microsequencer operate concurrently. The bus controller can
perform a read or write, or schedule a prefetch, while the microsequencer controls ef-
fective address calculation or sets condition codes.
The microsequencer can also request a bus cycle that the bus controller cannot per-
form immediately. When this happens, the bus cycle is queued, and the bus controller
runs the cycle when the current cycle is complete.

8.1.3.1 Prefetch Controller

The instruction prefetch controller receives an initial request from the microsequencer
to initiate prefetching at a given address. Subsequent prefetches are initiated by the
prefetch controller whenever a pipeline stage is invalidated, either through instruction
completion or through use of extension words. Prefetch occurs as soon as the bus is
free of operand accesses previously requested by the microsequencer. Additional
state information permits the controller to inhibit prefetch requests when a change in
instruction flow (e.g. a jump or branch instruction) is anticipated.
In a typical program, 10 to 25 percent of the instructions causes a change of flow. Each
time a change occurs, the instruction pipeline must be flushed and refilled from the
new instruction stream. If instruction prefetches, rather than operand accesses, were
given priority, many instruction words would be flushed unused, and necessary oper-
and cycles would be delayed. To maximize available bus bandwidth, the CPU32 will
schedule a prefetch only when the next instruction is not a change-of-flow instruction,
and when there is room in the pipeline for the prefetch.
8.1.3.2 Write-Pending Buffer
The CPU32 incorporates a single-operand write-pending buffer. The buffer permits the
microsequencer to continue execution after a request for a write cycle is queued in the
bus controller. The time needed for a write at the end of an instruction can overlap the
head cycle time for the following instruction, and thus reduce overall execution time.
Interlocks prevent the microsequencer from overwriting the buffer.
8.1.3.3 Microbus Controller
The microbus controller performs bus cycles issued by the microsequencer. Operand
accesses always have priority over instruction prefetches. Word and byte operands
are accessed in a single CPU-initiated bus cycle, although the external bus interface
may be required to initiate a second cycle when a word operand is sent to a byte-sized
external port. Long operands are accessed in two bus cycles, most significant word
first.
The instruction pipeline is capable of recognizing instructions that cause a change of
flow. It informs the bus controller when a change of flow is imminent, and the bus con-
troller refrains from starting prefetches that would be discarded due to the change of
flow.
CPU32
REFERENCE MANUAL
INSTRUCTION EXECUTION TIMING MOTOROLA
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