Timing Example 3: Negative Tails - Motorola CPU32 Reference Manual

8.2.3 Timing Example 3: Negative Tails

This example (Figure 8-7) shows how to use negative tail figures for branches and oth-
er change-of-flow instructions. In this example, bus speed is assumed to be four clocks
per access. Instruction three is at the branch destination.
Although the CPU32 has a two-word instruction pipeline, internal delay causes mini-
mum branch instruction time to be three bus cycles. The negative tail is a reminder that
an extra two clocks are available for prefetching a third word on a fast bus — on a slow-
er bus, there is no extra time for the third word.
1 2 3
CLOCK
BUS
BRANCH OFFSET
CONTROLLER
INSTRUCTION
CONTROLLER
EXECUTION
MOVEQ #7,D1
TIME
Figure 8-7 Example 3 — Branch Negative Tail
Example 3 illustrates three different aspects of instruction time calculation:
The branch instruction does not attempt to prefetch beyond the minimum number of
words needed for itself.
The negative tail allows execution to begin sooner than would a three-word pipeline.
There is a one-clock delay due to late arrival of the displacement at the CPU.
Only changes of flow require negative tail calculation, but the concept can be general-
ized to any instruction — only two words are required to be in the pipeline, but up to
three words may be present. When there is an opportunity for an extra prefetch, it is
made. A prefetch to replace an instruction can begin ahead of the instruction, resulting
in a faster processor.
CPU32
REFERENCE MANUAL
Instructions
MOVEQ#7, D1
BRA.WFARAWAY
MOVE.LD1, D0
4 5 6 7 8
OFFSET
MOVEQ
CALC
INSTRUCTION EXECUTION TIMING
9 0 1 2 3
FETCH NEXT
FETCH MOVE.L
INSTRUCTION
TAKEN
BRA.W FARAWAY
4 5 6 7 8
PREFETCH
MOVE
TAKEN
TO D0
MOVE.L D1,D0
MOTOROLA
9
8-9