Condition Tests - Motorola CPU32 Reference Manual

Table 4-9 System Control Operations (Continued)
Instruction
MOVEA
MOVEC
MOVES
ORI
RESET
RTE
STOP
LPSTOP
BKPT
BGND
CHK
CHK2
ILLEGAL
TRAP
TRAPcc
TRAPV
ANDI
EORI
MOVE
ORI

4.3.10 Condition Tests

Conditional program control instructions and the TRAPcc instruction execute on the
basis of condition tests. A condition test is the evaluation of a logical expression relat-
ed to the state of the CCR bits. If the result is one, the condition is true. If the result is
zero, the condition is false. For example, the T condition is always true, and the EQ
condition is true only if the Z bit condition code is true. Table 4-10 lists each condition
test.
MOTOROLA
4-12
Syntax Size
USP, An 32
An, USP 32
Rc, Rn 32
Rn, Rc 32
Rn, 〈ea〉
8, 16, 32
〈ea〉, Rn
#〈data〉, SR 16
none none
none none
#〈data〉 16
#〈data〉 none
Trap Generating
#〈data〉 none
none none
〈ea〉, Dn
16, 32
〈ea〉, Rn
8, 16, 32
none none
#〈data〉 none
none none
#〈data〉 16, 32
none none
Condition Code Register
#〈data〉, CCR 8
#〈data〉, CCR 8
〈ea〉, CCR
16
CCR, 〈ea〉
16
#〈data〉, CCR 8
INSTRUCTION SET
Operation
USP → An An → USP
Rc → Rn
Rn → Rc
Rn → Destination using DFC
Source using SFC → Rn
SR → SR
+
Data
Assert RESET line
(SP) → SR; SP + 2 → SP; (SP) → PC;
SP + 4 → SP;
restore stack according to format
Data → SR; STOP
Data → SR; interrupt mask → EBI; STOP
If breakpoint cycle acknowledged, then execute
returned operation word, else trap as illegal
instruction.
If background mode enabled, then enter
background mode, else format/vector offset →
– (SSP);
PC → 〉 (SSP); SR → 〉 (SSP); (vector) → PC
If Dn < 0 or Dn < (ea), then CHK exception
If Rn < lower bound or Rn > upper bound, then CHK
exception
SSP – 2 → SSP; vector offset → (SSP);
SSP – 4 → SSP; PC → (SSP);
SSP – 2 → SSP; SR → (SSP);
Illegal instruction vector address → PC
SSP – 2 → SSP; format/vector offset → (SSP);
SSP – 4 → SSP; PC → (SSP); SR → (SSP);
vector address → PC
If cc true, then TRAP exception
If V set, then overflow TRAP exception
Data • CCR → CCR
Data ⊕ CCR → CCR
Source → CCR
CCR → Destination
CCR → CCR
+
Data
CPU32
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