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The remainder of the stack contains the program counter of the next unexecuted in-
struction, the current status register, the address of the faulted memory location, and
the contents of the data buffer which was to be written to memory. This data is written
on the stack in the format depicted in Figure 6-3.
6.3.1.2 Type II: Prefetch, Operand, RMW, and MOVEP Faults
The majority of BERR exceptions are included in this category — all instruction
prefetches, all operand reads, all RMW cycles, and all operand accesses resulting
from execution of MOVEP (except the last write of a MOVEP Rn,〈ea〉 or the last write
of MOVEM, which are type I faults). The TAS, MOVEP, and MOVEM instructions ac-
count for all operand writes not considered released.
All type II faults cause an immediate exception that aborts the current instruction Any
registers that were altered as the result of an effective address calculation (i.e., postin-
crement or predecrement) are restored prior to processing the bus cycle fault.
The SSW for faults in this category contains the following bit pattern:
15
14
13
0
0
0
The trace pending bit is always cleared, since the instruction will be restarted upon re-
turn from the handler. Saving a pending exception on the stack would result in a trace
exception being taken prior to restarting the instruction. If the exception handler does
not alter the stacked SR trace bits, the trace is requeued when the instruction is start-
ed.
The breakpoint pending bits are stacked in the SSW, even though the instruction is
restarted upon return from the handler. This avoids problems with bus state analyzer
equipment that has been programmed to breakpoint only the first access to a specific
location, or to count accesses to that location. If this response is not desired, the ex-
ception handler can clear the bits before return. The RM, IN, RW, LG, FUNC, and SIZ
fields all reflect the type of bus cycle that caused the fault. If the bus cycle was an
RMW, the RM bit will be set and the RW bit will show whether the fault was on a read
or write.
6.3.1.3 Type III: Faults During MOVEM Operand Transfer
Bus faults that occur as a result of MOVEM operand transfer are classified as type III
faults. MOVEM Instruction prefetch faults are type II faults.
Type III faults cause an immediate exception that aborts the current instruction. None
of the registers altered during execution of the faulted instruction are restored prior to
execution of the fault handler. This includes any register predecremented as a result
of the effective address calculation or any register overwritten during instruction exe-
cution. Since postincremented registers are not updated until the end of an instruction,
the register retains its preinstruction value unless overwritten by operand movement.
The SSW for faults in this category contains the following bit pattern:
CPU32
REFERENCE MANUAL
12
11
10
9
0
B1
B0
0
EXCEPTION PROCESSING
8
7
6
5
RM
IN
RW
LG
4
3
2
SIZ
FUNC
MOTOROLA
0
6-17
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