Peripheral Commands; Status Bits; Processor Interrupts - Honeywell LEVEL 6 Operation Manual

LEVEL6
- -
-,
SYSTEM
I
I
I
~
MDC9101 SINGLE BOARD
: MULTIPLE DEVICE CONTROLLER.
~---------
-"I
I I I
: I
CRM9101
I I
--~
CARD READER
l------..l
I
ADAPTER!-4----------. ONE ADAPTER PER DEVICE.
i.. ________ ...:
L - - -
MAXIMUM CONFIGURATION OF
~
m""",""",",,,,,,,",
MDC9101.
CRU91 01/9102/91 03/91 04
CARD READER ISO/60Hz).
Figure 3-5. Card Reader System Configuration
TABLE 3-4. ASCII BIT RELATION TO BITS
IN SYSTEM MEMORY
SYSTEM MEMORY
ASCII Bit
Left Byte Right Byte
8
7
.
0
1
8
9
6 2 10
5
3
11
4
4 12
3 5 13
2 6 14
1 7
15
TABLE 3-5. COMMAND REPERTOIRE
Function
Type Command
Code
Output 03 Output Interrupt Control
01
Output Control
09
IOLD (Output Address and Range)
11
Output Configuration
Input
02
Input Interrupt Control
08 Input Memory Byte Address
OA Input Memory Module Address
OC Input Range
10
Input Configuration
18 Input Status
26 1
Input Device Identification Code
1 F or the card reader, the device number is 2008
CARD READER DEVICES
PERIPHERAL COMMANDS
Card reader operation is implemented by two
sets of instructions; the input and the output
commands (see Table 3-5). A discussion of these
commands will be found in the Series 60 (Level
6) Minicomputer Handbook, Order No. AS22.
STATUS BITS
Two status words are defined for the card
reader. Figure 3-6 illustrates the status bit
assignments and Table 3-6 defines the status bits
and the means by which each bit is reset.
Reaction of the MDC to card reader errors is as
follows:
o Errors occurring during data transfer are
indicated by a status report at the end of
the card.
o Errors occurring on I/O commands from
the central processor will set the appropri­
ate status bit and interrupt the processor
immediately (that is if interrupts are
allowed). The I/O command will be ac ­
knowledged normally and stored in MDC
memory but will cause no further action. If
interrupts are blocked (Level
=
0), the com­
mand in error will be used as if there were
no error.
PROCESSOR INTERRUPTS
Conditions that will cause a processor inter­
rupt are:
o Interrupt level non-zero and previous oper­
ation complete
o Interrupt level non-zero and error on I/O
command (see paragraph entitled Status
Bits)
o Completion of a stop I/O or 10LD comniand
o Termination of an 10LD comand due to a
device fault
If the interrupt level is zero due either to
initialize, master clear (or explicitly set to zero)
no interrupt will be issued for the cited condi­
tions. Status will be set at the proper time and the
NAK response from the MDC (when busy) may
be used to test for completion of the previous
operation.
AT04
3-5