Interface Processors - Cisco 7000 Hardware Installation And Maintenance

Physical Description

Interface Processors

An interface processor comprises a modular, self-contained interface board and one or more network
interface connectors in a single 11 x 14-inch unit. All interface processors support Online Insertion
and Removal (OIR), so you can install and remove them without opening the chassis and without
turning off the chassis power.
The RP and SP (or SSP), which are required system components, always reside in the RP and SP
slots. (See Figure 1-2.) The remaining five slots are available for any combination of the following
interface processors:
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The microcode on the SP (or SSP) and on each interface processor contains board-specific software
instructions. New features and enhancements to the system or interfaces are often implemented in
microcode upgrades.
The Cisco 7000 supports downloadable microcode, which enables you to download new microcode
images remotely and store them in Flash memory. You can then use software commands to load a
specific microcode image from Flash memory or to load the default microcode image from ROM.
Note
package. Overriding the bundle could possibly result in incompatibility between the various
interface processors in the system.
System software upgrades also can contain upgraded microcode images, which will load
automatically when the new software image is loaded. With this downloadable microcode feature,
you will probably never need to replace the microcode ROM on the board. If replacement is
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AIP—Asynchronous Transfer Mode (ATM) Interface Processor. For interface types and
specifications, refer to the section "AIP Interface Types" in the chapter "Preparing for
Installation."
CIP—Channel Interface Processor. Any combination of one or two bus and tag and/or one or two
Enterprise System Connection (ESCON) interfaces. For bus and tag and ESCON interface
configurations and specifications, refer to "Channel Attachment Connection Equipment" in the
chapter "Preparing for Installation."
EIP— High-speed (10 Mbps) Ethernet Interface Processor with two, four, or six AUI ports.
FEIP—For up to two 100BaseT, RJ-45 or Media Independent Interface (MII) ports. Each Fast
Ethernet interface on an FEIP can be configured for half duplex (HDX) or full duplex (FDX), for
a maximum aggregate bandwidth of 200 Mbps.
TRIP—High-speed (4 or 16 Mbps) Token Ring Interface Processor with two or four DB-9 ports.
FIP—High-speed (100 Mbps) FDDI Interface processor with one single attachment or dual
attachment port (PHY A/PHY B) in any combination of single-mode and multimode ports (such
as single-single, multi-single, and so forth).
FSIP—Fast (up to 8 Mbps, or 16 Mbps aggregate with 8 ports) Serial Interface Processor that
provides four or eight synchronous serial ports.
HIP—High-Speed (up to 52 Mbps) Serial Interface (HSSI) Interface Processor with a single
HSSI port.
MIP—MultiChannel Interface Processor with up to two channelized T1 interfaces that operate
at T1 speed: up to 1.544 Mbps.
We strongly recommend that the microcode bundled with the system software be used as a