Configuring Timing (Clock) Signals - Cisco 7000 Hardware Installation And Maintenance

Installing and Configuring Processor Modules

Configuring Timing (Clock) Signals

To use an FSIP port as a DCE interface, you must connect a DCE port adapter cable and set the clock
speed with the clockrate command. You must also set the clock rate to perform a loopback test. This
section describes how to use software commands to set the clock rate on a DCE port and, if
necessary, how to invert the clock to correct a phase shift between the data and clock signals.
Setting the Clock Rate
All DCE interfaces require a noninverted internal transmit clock signal, which is generated by the
FSIP. The default operation on an FSIP DCE interface is for the DCE device (FSIP) to generate its
own clock signal (TxC) and send it to the remote DTE. The remote DTE device returns the clock
signal to the DCE (FSIP port). When using DCE interfaces, you must connect a DCE-mode adapter
cable to the port and specify the rate of the internal clock with the clockrate configuration command
followed by the bits-per-second value. In the following example, the top serial interface on an FSIP
in interface processor slot 3 (3/0) is defined as having a clockrate of 2 Mbps.
Following are acceptable clockrate settings:
1200, 2400, 4800, 9600, 19200, 38400, 56000, 64000, 72000, 125000, 148000, 500000, 800000,
1000000, 1300000, 2000000, 4000000
Speeds above 64 kbps (64000) are not appropriate for EIA/TIA-232; use EIA/TIA-449 on faster
interfaces. Note that the faster speeds might not work if your cable is too long. If you change an
interface from DCE to DTE, use the no clockrate command to remove the clock rate.
The FSIP ports support full duplex operation at DS1 (1.544 Mbps) and E1 (2.048 Mbps) speeds.
Each four-port module (see the section "Fast Serial Interface Processor (FSIP)" in the chapter
"Product Overview") can support an aggregate bandwidth of 6.132 Mbps.
Because each four-port module shares a processor, you can delegate bandwidth to a single port and
leave the other ports idle to optimize speed and bandwidth on a single interface. For example, you
can configure four T1 interfaces on a module (one T1 on each port) such that they do not exceed
6.132 Mbps, or you can configure one port to operate at up to 6.132 Mbps, and leave the remaining
three ports shut down. The type of electrical interface, the amount of traffic processed, and the types
of external data service units (DSUs) connected to the ports affect actual rates.
Inverting the Clock Signal
Systems that use long cables may experience high error rates when operating at the higher speeds.
Slight variances in cable length, temperature, and other factors can cause the data and clock signals
to shift out of phase. Inverting the clock can often correct this shift. The invert-transmit-clock
configuration command inverts the TxC clock signal for DCE interfaces. This prevents phase
shifting of the data with respect to the clock.
To change the clock back to its original phase use the no invert-transmit-clock command. In the
example that follows, the clock is inverted for the top serial port on an FSIP in interface processor
slot 3:
5-206 Cisco 7000 Hardware Installation and Maintenance
7000# configure terminal
interface serial 3/0
clockrate 2000000
^z
7000# configure terminal
interface serial 3/0
invert-transmit-clock
^z