Flash Control/Status Register (Flcr) (Cpu Mode) - Fujitsu FR60 Hardware Manual

CHAPTER 17 FLASH MEMORY
17.2.1

Flash Control/Status Register (FLCR) (CPU mode)

The flash control/status register (FLCR) (CPU mode) indicates the operating status of
flash memory. The FLCR controls writing to flash memory. The FLCR can be accessed
only in CPU mode.
Do not use read modify write instructions to access this register.
■ Configuration of the Flash Control/Status Register (FLCR) (CPU Mode)
The configuration of the flash control/status register (FLCR) (CPU mode) is shown below.
[Bit 7] Reserved: Reserved bit
Always set this bit to "0."
[Bits 6 and 5] Reserved: Reserved bits
Always set these bits to "1."
[Bit 4] RDYEG
The end of the flash memory automatic algorithm (i.e., write, erase) sets this bit to "1".
Reading clears this bit.
Value
• This bit is initialized to "0" by a reset.
540
Address : 00007000
H
R/W
Initial value→
0 The end of the automatic algorithm has not been detected.
1 The end of the automatic algorithm has been detected.
7 6 5 4
- - - RDYEG RDY
R/W R/W R
(0) (1) (1) (0)
Explanation
3 2 1
- WE
R R/W R/W R/W
(X) (0) (0) (0)
0
-