Fujitsu FR60 Hardware Manual page 491

• Transfer mode
Demand transfer, burst transfer, step transfer, and block transfer
Note: The MB91F353A/351A/352A/353A do not support demand transfer.
Addressing mode: 32-bit full addressing (increment/decrement/fixed)
(The address increment/decrement range is from -255 to + 255.)
Data types: Byte, halfword, and word length
Single shot/reload selectable
■ Overview of the DMAC Registers
Figure 16.1-1 provides an overview of the DMAC registers.
ch 0 control/status register A
ch 0 control/status register B
ch 1 control/status register A
ch 1 control/status register B
ch 2 control/status register A
ch 2 control/status register B
ch 3 control/status register A
ch 3 control/status register B
ch 4 control/status register A
ch 4 control/status register B
All-channel control register
ch 0 transfer source address register
ch 0 transfer destination address register
ch 1 transfer source address register
ch 1 transfer destination address register
ch 2 transfer source address register
ch 2 transfer destination address register
ch 3 transfer source address register
ch 3 transfer destination address register
ch 4 transfer source address register
ch 4 transfer destination address register
Figure 16.1-1 Overview of the DMAC Registers
DMACA0 00000200
DMACB0 00000204
DMACA1 00000208
DMACB1 0000020C
DMACA2 00000210
DMACB2 00000214
DMACA3 00000218
DMACB3 0000021C
DMACA4 00000220
DMACB4 00000224
DMACR
DMASA0 00001000
DMADA0 00001004
DMASA1 00001008
DMADA1 0000100C
DMASA2 00001010
DMADA2 00001014
DMASA3 00001018
DMADA3 0000101C
DMASA4 00001020
DMADA4 00001024
(bit)
31 24
H
H
H
H
H
H
H
H
H
H
00000240
H
H
H
H
H
H
H
H
H
H
H
23 16 15 08 07 00
473