Fujitsu FR60 Hardware Manual page 624

APPENDIX
Table D-2 Addition and Subtraction
Mnemonic
ADD Rj, Ri
*ADD #s5, Ri
ADD #u4, Ri
ADD2 #u4, Ris
ADDN Rj, Ri
ADDN Rj, Ri
*ADDN #s5, Ri
ADDN #u4, Ri
ADDN2 #u4, Ri
SUB Rj, Ri
SUBC Rj, Ri
SUBN Rj, Ri
Table D-3 Comparison
Mnemonic
CMP Rj, Ri
*CMP #s5, Ri
CMP #u4, Ri
CMP2 #u4, Ri
Table D-4 Logic Operations
Mnemonic
AND Rj, Ri
AND Rj, @Ri
ANDH Rj, @Ri
ANDB Rj, @Ri
OR Rj, Ri
OR Rj, @Ri
ORH Rj, @Ri
ORB Rj, @Ri
EOR Rj, Ri
EOR Rj, @Ri
EORH Rj, @Ri
EORB Rj, @Ri
606
Type OP CYCLE
A A6 1
C' A4 1
C A4 1
C A5 1
A A7 1
A A2 1
C' A0 1
C A0 1
C A1 1
A AC 1
A AD 1
A AE 1
Type OP CYCLE
A AA 1
C' A8 1
C A8 1
C A9 1
Type OP CYCLE
A 82
A 84 1+2a
A 85 1+2a
A 86 1+2a
A 92
A 94 1+2a
A 95 1+2a
A 96 1+2a
A 9A
A 9C 1+2a
A 9D 1+2a
A 9E 1+2a
NZVC Operation
→
CCCC
Ri + Rj Ri
→
CCCC
Ri + s5 Ri
CCCC
Ri + extu(i4)
CCCC
Ri + extu(i4)
→
CCCC
Ri + Rj + c
→
----
Ri + Rj Ri
→
----
Ri + s5 Ri
----
Ri + extu(i4)
----
Ri + extu(i4)
→
CCCC
Ri - Rj Ri
→
CCCC
Ri - Rj - c
→
----
Ri - Rj Ri
NZVC Operation
CCCC Ri - Rj
CCCC Ri - s5
CCCC Ri - extu(i4)
CCCC Ri - extu(i4)
NZVC
1 CC-- Ri &= Rj
CC-- (Ri) &= Rj
CC-- (Ri) &= Rj
CC-- (Ri) &= Rj
1 CC-- Ri | = Rj
CC-- (Ri) | = Rj
CC-- (Ri) | = Rj
CC-- (Ri) | = Rj
1 CC-- Ri ^ = Rj
CC-- (Ri) ^ = Rj
CC-- (Ri) ^ = Rj
CC-- (Ri) ^ = Rj
Remarks
The assembler treats the highest-
order bit as the sign.
→
Zero extension
Ri
→
Minus extension
Ri
Addition with carry
Ri
The assembler treats the highest-
order bit as the sign.
→
Zero extension
Ri
→
Minus extension
Ri
Addition with carry
Ri
Remarks
The assembler treats the highest-
order bit as the sign.
Zero extension
Minus extension
Operation
Word
Word
Halfword
Byte
Word
Word
Halfword
Byte
Word
Word
Halfword
Byte
Remarks