Fujitsu FR60 Hardware Manual page 238

CHAPTER 4 EXTERNAL BUS INTERFACE
Generally, when connecting asynchronous memory to which burst/page access cannot be applied, it is best
to set the burst length to "1" (single access). Conversely, when memory whose burst/page access cycle is
short is connected, it is better to set the burst length to any value other than "1" (single access). In this case,
it is best to make the setting so that 8 bytes (half of the buffer) are read in one read operation according to
the bus width. However, the optimum condition varies with the frequency of external access and varies
with the frequency divide-by rate setting of the external access clock.
■ Reading from the Prefetch Buffer
Data stored in the prefetch buffer is read in response to access from the internal bus if an address matches,
and no external access is performed. In reading from the buffer, addresses can be hit (up to 16 bits) if they
are in the forward direction but not continuous, so that a second read from the external bus is avoided, if
possible, even for a short forward branch.
If the address currently being accessed for prefetch matches during access from the internal bus, a wait
signal is returned internally before data is captured after prefetch access is completed. In this case, no
buffer error occurs.
If an address in the prefetch buffer matches when a read is performed for DMA transfer, data in the
prefetch buffer is not used, and instead, external data is read by the external bus. In this case, a buffer error
occurs. The prefetch is not continued and no prefetch access is performed until a new external access
operation to a prefetch-enabled area occurs.
■ Clearing/Updating the Prefetch Buffer
If either of the following conditions is met, the prefetch buffer is completely cleared:
• If "1" is written to the PCLR bit of the TCR register
• If a buffer read error occurs.
• If a buffer write hit occurs.
Only part of the prefetch buffer is cleared when the following condition is met:
• If a buffer read hit occurs
In this case, only the part of the buffer before the hit address is cleared.
A buffer read error is if any of the following events occurs:
• When no address is found in the buffer that matches in an to read from a prefetch-enabled area.
In this case, the external bus is accessed again. Data read in this case is not stored in the buffer, but the
prefetch access is started from the subsequent address to store addresses in the buffer.
• In an access to read from a prefetch-enabled area with a read modified system instruction.
In this case, the external bus is accessed again. Data read in this case is not stored in the buffer. Also, no
prefetch access is performed (This is because data is written to the next address).
• In an access to read from a prefetch-enabled area for DMA transfer.
In this case, the external bus is accessed again. Data read in this case is not stored in the buffer. Also, no
prefetch access is performed.
A buffer write hit is as follows:
• When the address of just one byte that matches is found in the buffer in an access to write to a prefetch-
enabled area.
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