Fujitsu FR60 Hardware Manual page 157

[Circuits that stop in the sleep state]
• Program execution on the CPU
• Data cache
• Bit search module (enabled if DMA transfer occurs)
• Various built-in memory (enabled if DMA transfer occurs)
• Internal and external buses (enabled if DMA transfer occurs)
[Circuits that do not stop in the sleep state]
• Oscillation circuit
• PLL that has been enabled
• Clock generation controller
• Interrupt controller
• Peripheral circuit
• DMA controller
• DSU
• Watch timer
• Main clock oscillation stabilization wait timer
[Sources of return from the sleep state]
• Generation of a valid interrupt request
If an interrupt request with an interrupt level other than interrupt disabled (1F
cleared and the RUN state (normal operation state) is entered.
To prevent sleep mode from being cleared even when an interrupt request occurs, set interrupt disabled
(1F
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• Generation of a settings initialization reset (INIT) request
If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT) state is
unconditionally entered.
• Generation of an operation initialization reset (RST) request
If an operation initialization reset (RST) request occurs, the operation initialization reset (RST) state is
unconditionally entered.
Note:
For information about the priority of sources, see "Priority of State Transition Requests" in Section
"3.11.1 Device States and State Transitions".
[synchronous standby operations]
Synchronous standby operation is enabled with bit 8 (SYNCS bit) in the time - base counter control register
(TBCR) set to "1". Transition to the sleep state does is not caused only by a write to the SLEEP bit.
Transition to the sleep state occurs when the STCR register is read after that.
To enter the sleep mode, be sure to use the sequence in (Transition to sleep mode).
) as the interrupt level in the corresponding ICR.
) occurs, sleep mode is
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