Fujitsu FR60 Hardware Manual page 620

APPENDIX
Table C-3 Pin States in Single-Chip Mode (2 / 2)
Pin No. Port name
120 PI4
121 PI5
106 to 113 PJ0 to PJ7
98 to 105 PK0 to PK7
94 PL0
95 PL1
87 PM0
88 PM1
89 PM2
90 PM3
91 PM4
92 PM5
81 to 86 PN0 to PN5
71 to 78 PO0 to PO7
67 to 70 PP0 to PP3
50 to 61 -
47 to 49 -
* : The input enabled state for INT0 to INT15 means that input is enabled during output Hi-Z state. This pin can be used to return from the stop state.
602
At initialization (INIT)
Specified-func-
tion name
Function
name
SO1 PI4
SCK1 PI5
INT8 to INT15
PJ0 to PJ7
*
INT0 to INT5
INT6/FRCK
PK0 to PK7
INT7/ATG
*
SDA PL0
SCL PL1
SI6/AIN0/TRG0 PM0
SO6/BIN0/
PM1
TRG1
SCK6/ZIN0/
PM2
TRG2
SI7/AIN1/TRG3 PM3
SO7/BIN1/
PM4
TRG4
SCK7/ZIN1/
PM5
TRG5
PPG0 to PPG5 PN0 to PN5
OC0 to OC7 PO0 to PO7
TOT0 to TOT3 PP0 to PP3
AN0 to AN11 AN0 to AN11
DA0 to DA2 DA0 to DA2
Initial value
Sleep mode, sub-
clock sleep mode
Internal ROM
mode vector
(MD2 to 0 = 000)
Hi-Z output/input Previous state
enabled maintained
Input disabled
"L" level output
P: General-purpose port selected, F: Specified function selected
Stop mode, watch mode
HIZ=0 HIZ=1
Hi-Z output/
Previous state
input always
maintained
"0"
P: Previous state P: Hi-Z output
maintained F: Input
F: Input enabled enabled
P: Previous state P: Hi-Z output
maintained F: Input
F: Input enabled enabled
Hi-Z output/
Previous state
input always
maintained
"0"
Input disabled Input disabled
"L" level
"L" level output
output
Re-marks