Big Endian Bus Access - Fujitsu FR60 Hardware Manual

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CHAPTER 4 EXTERNAL BUS INTERFACE

Big Endian Bus Access

Except for the CS0 area, the FR family can switch between the big endian method and

little endian method for each chip select area. When the LEND bit of the ACR register is

set to "0", the chip select area is treated as big endian.

Normally, the FR family executes external bus access using big endian.

■ Big Endian Data Format

Figure 4.4-3 shows the relationship between the internal register and external data bus based on the data

format of word access (when the LD and ST instructions are executed).

Figure 4.4-3 Word Access (When LD and ST Instructions Executed)

Figure 4.4-4 shows the relationship between the internal register and external data bus based on the data

format of halfword access (when the LDUH and STH instructions are executed).

Figure 4.4-4 Halfword Access (When LDUH and STH Instructions Executed)

Internal register

a) Output address low-order

Internal register External bus

External bus

b) Output address low-order

Internal register External bus

Mb91350a series