Fujitsu FR60 Hardware Manual page 645

DMAC Interrupt Control Output
Interrupts That Enable DMAC Interrupt Control
Outputs .............................................. 514
DMAC Interrupt Source Clear Register
DMAC Interrupt Source Clear Register (SRCL)
.......................................................... 418
DMAC Register
Overview of the DMAC Registers ..................... 473
DMACA
Functions of the DMACA0 to 4 Bits .................. 476
DMACB
Functions of the DMACB0 to 4 Bits .................. 482
DMACR
Functions of the DMACR Bits .......................... 490
DMADA
Functions of the DMASA0 to 4 and DMADA0 to 4
Bits.................................................... 488
DMASA
Functions of the DMASA0 to 4 and DMADA0 to 4
Bits.................................................... 488
Double Type
Use of the Double Type and Long Double Type
............................................................ 40
DRCL
DRCL ............................................................. 398
DREQ
Minimum Effective Pulse Width of the DREQ Pin
Input. ................................................. 518
Negate Timing of the DREQ Pin Input when a
Demand Transfer Request is Stopped
.......................................................... 518
Timing of the DREQ Pin Input for Continuing
Transfer Over the Same Channel .......... 520
DREQx
Timing of DREQx Pin Input ............................. 530
DRLR
DRLR: Data RAM Limit Control Register
(D-Bus RAM Limit Control Register)
.......................................................... 577
DSTP
Timing of the DSTP Pin Input........................... 520
E
EIRRn
Bit Configuration of the External Interrupt Request
Register (EIRRn) ................................ 346
EIT
EIT Causes........................................................ 72
EIT Interrupt Levels ........................................... 73
EIT Vector Table ............................................... 80
Features of EIT .................................................. 72
Priority of EIT Causes to Be Accepted ................. 84
Return from EIT ................................................ 72
ELVRn
Bit Configuration of External Level Register (ELVRn)
..........................................................347
Emulator
Emulator and Monitor Debuggers ........................43
Enabling Operation
Enabling Operation for All Channels ..................508
Endian Area
Connection Between the MB91350A Device and the
Endian Areas.......................................200
ENIRn
Bit Configuration of Enable Interrupt Request
Register (ENIRn).................................345
Erase
Overview of Flash Memory Write/Erase .............557
Sector Erase Procedure......................................562
Temporarily Stop Erase.....................................551
Erasing Data
Erasing Data (Chip Erase) From Flash Memory
..........................................................561
Error
Bus Error .........................................................466
Communication Error that Causes No Error ........467
Coprocessor Error Trap .......................................89
Non-detection of Errors.......................................42
Occurrence of an Address Error .........................513
Example
Example of Connection with External Devices
..........................................................196
Example of Receive Data ..................................469
Example of Setting ASRs and ASZ[3:0] .............186
Example of Setting Baud Rates and U-TIMER Reload
Values ................................................409
Example of Slave Address and Data Transfer
..........................................................468
Example of System Construction
(Using Mode 1) ...................................407
Example of Using the Hold Request Cancellation
Request Function (HRCR)....................338
Examples of Methods Used to Perform All-L and
All-H PPG Output ...............................319
Examples of Operation (Simple Waveforms).......529
Examples of Serial Programming Connections
..........................................................570
Explanation
Explanation of Terms Used in the Pin State
Lists ...................................................597
Explanation of the Main Clock Oscillation
Stabilization Wait Timer Register..........150
External Bus
Bus Mode 1 (Internal-ROM/External-bus Mode)
............................................................91
Bus Mode 2 (External-ROM/External-bus Mode)
............................................................91
Setting the External Bus ......................................33
INDEX
627