Fujitsu FR60 Hardware Manual page 421

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Receive operation in Mode 0
The PE, ORE, FRE, and RDRF flags are set when the last stop bit is detected after a receive transfer is
completed, causing an interrupt request to be generated for the CPU. The SIDR data is invalid while PE,
ORE, and FRE are active.
Figure 14.1-4 shows the timing for setting ORE, FRE, and RDRF in Mode 0.
Figure 14.1-4 Timing for Setting ORE, FRE, and RDRF (Mode 0)
Data
PE, ORE,FRE
RDRF
Receive interrupt
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Receive operation in Mode 1
The ORE, FRE, and RDRF flags are set when the last stop bit is detected after a receive transfer is
completed, causing an interrupt request to be generated for the CPU. The data indicating an address or the
data in Bit 9 is invalid because the length of data that can be received is 8 bits. The SIDR data is invalid
while ORE and FRE are active.
Figure 14.1-5 shows the timing for setting ORE, FRE, and RDRF in Mode 1.
Figure 14.1-5 Timing for Setting ORE, FRE, and RDRF (Mode 1)
Data
ORE,FRE
RDRF
Receive interrupt
D7
D6
D6 Address/Data
Stop
Stop
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