Fujitsu FR60 Hardware Manual page 386

CHAPTER 12 A/D CONVERTER
[Bit 6] INT (interrupt)
This INT bit is set when conversion ends. (It is set when conversion of the input on a channel ends in
single conversion mode or when conversion of all input on all the specified channels ends in scan
conversion mode.)
Value
The INT bit is cleared by writing "0" to it or by clearing of a DMA transfer interrupt, or at the start of
conversion or by a reset.
Writing "1" to the INT bit is invalid.
If a read modify write instruction is issued, "1" is always read from the INT bit.
[Bit 5] INTE (interrupt enable)
The INTE bit specifies whether to enable or disable the interrupt that indicates the end of conversion.
Value
Set the INTE bit to "1" for automatic transfer by DMA.
The INTE bit is initialized to "0" by a reset.
[Bit 4] (unused)
This bit is not used.
[Bits 3 and 2] STS1 and STS0 (start select)
The STS1 and STS0 bits specify the A/D converter activation source.
STS1
0
0
1
1
In the mode in which multiple types of activation sources are allowed, the A/D converter is started by
the source that occurs first.
All of the activation sources that occur while the A/D converter is operating (BUSY = 1) are ignored.
(This means the A/D converter cannot be restarted during operation.)
To restart the A/D converter, stop the A/D conversion by writing "0" to the BUSY bit, then restart it.
When an external trigger is used for starting, the falling edge is detected. When the reload timer is used
for starting, the rising edge is detected.
The STS1 and STS0 bits are cleared to "00" by a reset.
368
0 Interrupt request not found
1 Interrupt request found
0 Interrupt disabled
1 Interrupt enabled
STS0
0
1
0
1
Meaning
Meaning
Start by software
Start by external pin trigger or software
Start by reload timer or software
Start by external pin trigger, reload timer, or software
Function