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CHAPTER 23 2M/3M BIT FLASH MEMORY
23.3 Flash memory Control Status Register (FMCS)
The flash memory control status register (FMCS) is used for write/erase operations on
flash memory via the registers in the flash memory interface circuit.
■
Flash memory control status register (FMCS)
The diagram below shows the bit configuration of the flash memory control status register
(FMCS).
The bits in the flash memory control status register (FMCS) have the following functions.
[bit7] INTE: INTerrupt Enable
This bit is used to enable or disable an interrupt request to the CPU due to the end of a flash
memory write/erase access.
If the INTE bit is set to "1" and the RDYINT bit is set to "1", an interrupt is issued to the CPU.
If the INTE bit is set to "0", no interrupt is issued.
0
1
[bit6] RDYINT: ReaDY INTerrupt
This bit indicates the operation state of the flash memory.
At the end of a flash memory write/erase operation, this bit is normally set to "1". When this
bit remains "0" after the end of a flash memory write/erase operation, further flash memory
write/erase operations are not allowed. Only after this bit has been set to "1" at the end of the
write/erase operations is the next write/erase operation for flash memory allowed.
This bit is cleared by writing "0". Writing "1" has no effect. This bit is set to "1" according to
the end timing of the flash memory automatic algorithm (Refer to Section "23.4 Method for
Starting the Flash Memory's Automatic Algorithm"). Read-modify-write (RMW) instructions
always read "1" for this bit.
0
1
480
bit
7
Address: 0000AE
INTE RDYINT
H
Read/Write
(R/W) (R/W) (R/W)
Initial value
(0)
Interrupt at the end of write/erase operations prohibited
Interrupt at the end of write/erase operations allowed
Write/erase operation in progress
End of write/erase operation (interrupt request generation)
6
5
4
3
WE
RDY Reserved LPM1 Reserved LPM0
(W)
(W)
(0)
(0)
(X)
(0)
2
1
0
(R/W)
(W)
(R/W)
(0)
(0)
(0)
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