Hitachi H8S/2633 Hardware Manual page 883

DMAC and DTC Module Stop: Depending on the operating status of the DMAC and DTC, the

MSTPA7 and MSTPA6 bits may not be set to 1. Setting of the DMAC or DTC module stop mode

should be carried out only when the respective module is not activated.

For details, refer to section 8, DMA Controller and section 9, Data Transfer Controller (DTC).

On-Chip Supporting Module Interrupt: Relevant interrupt operations cannot be performed in

module stop mode. Consequently, if module stop mode is entered when an interrupt has been

requested, it will not be possible to clear the CPU interrupt source or the DMAC and DTC

activation source. Interrupts should therefore be disabled before entering module stop mode.

Writing to MSTPCR: MSTPCR should only be written to by the CPU.

Software Standby Mode

Software Standby Mode

A transition is made to software standby mode when the SLEEP instruction is executed when the

SBYCR SSBY bit = 1 and the LPWRCR LSON bit = 0, and the TCSR (WDT1) PSS bit = 0. In

this mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of

the CPU's internal registers, RAM data, and the states of on-chip supporting modules other than

the SCI, A/D converter, and 14-bit PWM, and I/O ports, are retained. Whether the address bus and

bus control signals are placed in the high-impedance state.

In this mode the oscillator stops, and therefore power dissipation is significantly reduced.

Exiting Software Standby Mode

Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ7), or by

means of the RES pin, MRES pin or STBY pin.

(1) Exiting Software Standby Mode with an Interrupt

When an NMI or IRQ0 to IRQ7 interrupt request signal is input, clock oscillation starts, and

after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks are supplied to

the entire chip, software standby mode is exited, and interrupt exception handling is started.

When exiting software standby mode with an IRQ0 to IRQ7 interrupt, set the corresponding

enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ7

is generated. Software standby mode cannot be exited if the interrupt has been masked on the

CPU side or has been designated as a DTC activation source.