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TCSR0—Timer Control/Status Register 0
Bit
:
OVF
Initial value
:
R/(W) *
R/W
:
Overflow flag
0
[Clearing]
When 0 is written to OVF bit after reading TCSR when OVF=1.
1
[Setting]
When TCNT overflows (changes from H'FF to H'00).
When internal reset request generation is selected in watchdog timer mode,
OVF is cleared automatically by the internal reset.
Notes: 1. Only 0 can be written to these bits (to clear these flags).
2. TCSR is write-protected by a password to prevent accidental overwriting.
For details see section 15.2.5, Notes on Register Access.
1088
7
6
WT/IT
TME
0
0
R/W
R/W
Timer enable
0 Initializes TCNT to H'00 and disables the counting operation.
1 TCNT performs counting operation.
Timer mode select
0
1
Note: * See Section 15.2.3, "Reset control/status register (RSTCSR)" for
details of when TCNT overflows in watchdog timer mode.
H'FF74 (W), H'FF74 (R)
5
4
—
0
1
—
Clock select 2 to 0
WDT0 input clock select
CKS2
CKS1
0
0
1
1
0
1
Note: The overflow cycle starts when TCNT starts counting from
H'00 and ends when an overflow occurs.
Interval timer mode: Interval timer interrupt (WOVI) request
sent to CPU when overflow occurs at TCNT.
Watchdog timer mode: WDTOVF signal output externally
when overflow occurs at TCNT. *
3
2
—
CKS2
CKS1
1
0
—
R/W
CKS0
Clock
0
ø/2
1
ø/64
0
ø/128
1
ø/512
0
ø/2048
1
ø/8192
0
ø/32768
1
ø/131072
WDT0
1
0
CKS0
0
0
R/W
R/W
Overflow cycle
(when ø= 25MHz)
20.4 µs
652.8 µs
1.3 ms
5.2 ms
20.9 ms
83.6 ms
334.2 ms
1.34 s
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