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Bits 6 to 4—IrDA clock select 2 to 0 (IrCKS2 to IrCKS0): When the IrDA function is enabled,
these bits set the width of the High pulse when encoding the IrTxD output pulse.
Bit 6
Bit 5
IrCKS2
IrCKS1
0
0
1
1
0
1
Bits 3 to 0—Reserved: These bits are always read as 0 and cannot be modified.
16.2.11 Module Stop Control Registers B and C (MSTPCRB, MSTPCRC)
MSTPCRB
Bit
:
MSTPB7
Initial value
:
R/W
:
MSTPCRC
Bit
:
MSTPC7
Initial value
:
R/W
:
MSTPCRB and MSTPCRC are 8-bit readable/writable registers that perform module stop mode
control.
Setting any of bits MSTPB7 to MSTBP5 and MSTPC7 and MSTPC6 to 1 stops SCI0 to SCI4
operating and enter module stop mode on completion of the bus cycle. For details, see section
24.5, Module Stop Mode.
Bit 4
IrCKS0
Description
0
B×3/16 (three sixteenths of bit rate)
1
ø/2
0
ø/4
1
ø/8
0
ø/16
1
ø/32
0
ø/64
1
ø/128
7
6
MSTPB6
MSTPB5
1
1
R/W
R/W
7
6
MSTPC6
MSTPC5
1
1
R/W
R/W
5
4
MSTPB4
MSTPB3
1
1
R/W
R/W
5
4
MSTPC4
MSTPC3
1
1
R/W
R/W
3
2
MSTPB2
MSTPB1
1
1
R/W
R/W
3
2
MSTPC2
MSTPC1
1
1
R/W
R/W
(Initial value)
1
0
MSTPB0
1
1
R/W
R/W
1
0
MSTPC0
1
1
R/W
R/W
613
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