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DMAWER—DMA Write Enable Register
Bit
:
DMAWER
:
Initial value
:
R/W
:
Write enable 1B
0
Disables writing to all DMACR1B bits, DMABCR bits 11, 7, and 3, and
DMATCR bit 5.
1
Enables writing to all DMACR1B bits, DMABCR bits 11, 7, and 3, and
DMATCR bit 5.
Write enable 1A
0
1
DMATCR—DMA Terminal Control Register
Bit
:
DMATCR
:
Initial value
:
R/W
:
7
6
—
—
0
0
—
—
Disables writing to all DMACR1A bits, and DMABCR bits 10, 6, and 2.
Enables writing to all DMACR1A bits, and DMABCR bits 10, 6, and 2.
Write enable 0B
0
Disables writing to all DMACR0B bits, DMABCR bits 9, 5, and 1, and
DMATCR bit 4
1
Enables writing to all DMACR0B bits, DMABCR bits 9, 5, and 1, and
DMATCR bit 4.
Write enable 0A
0
Disables writing to all DMACR0A bits, and DMABCR bits 8, 4, and 0.
1
Enables writing to all DMACR0A bits, and DMABCR bits 8, 4, and 0.
7
6
—
—
TEE1
0
0
—
—
H'FF60
5
4
—
—
WE1B
0
0
—
—
R/W
H'FF61
5
4
TEE0
0
0
R/W
R/W
Transfer end pin enable 0
0
1
Transfer end pin enable 1
0
Disables TEND1 pin output.
1
Enables TEND1 pin output.
3
2
1
WE1A
WE0B
0
0
0
R/W
R/W
(Initial value)
(Initial value)
(Initial value)
3
2
—
—
—
0
0
—
—
—
Disables TEND0 pin output.
Enables TEND0 pin output.
DMAC
0
WE0A
0
R/W
(Initial value)
DMAC
1
0
—
0
0
—
1081
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