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Hitachi H8S/2633 Hardware Manual page 1068

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TIER0—Timer Interrupt Enable Register 0
TIER3—Timer Interrupt Enable Register 3
Channel 0: TIER0
Channel 3: TIER3
Bit
:
TTGE
Initial value
:
R/W
:
1056
7
6
0
1
R/W
Overflow interrupt enable
0
TCFV interrupt request (TCIV) disabled.
1
TCFV interrupt request (TCIV) enabled.
A/D conversion start request enable
0
A/D conversion start request generation disabled.
1
A/D conversion start request generation enabled.
TGR interrupt enable D
0
1
TGR interrupt enable C
H'FF14
H'FE84
5
4
TCIEV
TGIED
0
0
R/W
TGFD bit interrupt request (TGID) disabled.
TGFD bit interrupt request (TGID) enabled.
0
TGFC bit interrupt request (TGIC) disabled.
1
TGFC bit interrupt request (TGIC) enabled.
TGR interrupt enable B
0
TGFB bit interrupt request (TGIB) disabled
1
TGFB bit interrupt request (TGIB) enabled
TGR interrupt enable A
0
TGFA bit interrupt request (TGIA) disabled.
1
TGFA bit interrupt request (TGIA) enabled.
3
2
TGIEC
TGIEB
0
0
R/W
R/W
TPU0
TPU3
1
0
TGIEA
0
0
R/W
R/W

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