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TMDR1—Timer Mode Register 1
TMDR2—Timer Mode Register 2
TMDR4—Timer Mode Register 4
TMDR5—Timer Mode Register 5
Channel 1: TMDR1
Channel 2: TMDR2
Channel 4: TMDR4
Channel 5: TMDR5
Bit
:
Initial value
:
R/W
:
Mode 3 to 0
Note: 1.
7
6
—
—
1
1
—
—
MD3*
1
MD2*
2
0
0
1
1
*
MD3 is a reserved bit. Only write 0 to this bit.
2.
Phase calculation mode cannot be set for channels 0 and 3.
Only write 0 to MD2.
H'FF21
H'FF31
H'FE91
H'FEA1
5
4
—
—
MD3
0
0
—
—
R/W
MD1
MD0
0
0
Normal operation
1
Reserved
1
0
PWM mode 1
1
PWM mode 2
0
0
Phase calculation mode 1
1
Phase calculation mode 2
1
0
Phase calculation mode 3
1
Phase calculation mode 4
*
*
—
3
2
MD2
MD1
0
0
R/W
R/W
* : Don't care
TPU1
TPU2
TPU4
TPU5
1
0
MD0
0
0
R/W
1061
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