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2
ICCR0—I
C Bus Control Register
2
ICCR1—I
C Bus Control Register
Bit
:
7
ICE
Initial value
:
0
R/W
:
R/W
2
I
C Bus Interface Enable
0 I
I
1 I
the bus)
ICMR and ICDR can be accessed
Note: * Only 0 can be written, for flag clearing.
1090
6
5
IEIC
MST
0
0
R/W
R/W
2
I
C Bus Interface Interrupt Enable
0 Interrupts disabled
1 Interrupts enabled
2
C bus interface module disabled, with SCL and SDA signal pins set to port function
2
C bus interface module internal states initialized SAR and SARX can be accessed
2
C bus interface module enabled for transfer operations (pins SCL and SCA are driving
H'FF78
H'FF80
4
3
TRS
ACKE
0
0
R/W
R/W
I
Note: * For details see section 18.2.5, I
Bus busy
0 Bus is free
[Clearing condition]
When a stop condition is detected
1 Bus is free
[Clearing condition]
When a stop condition is detected
Acknowledge bit judgement selection
0 The value of the acknowledge bit is ignored, and
continuous transfer is performed
1 If the acknowledge bit is 1, continuous transfer is
interrupted
Master/slave select, transmit/receive select
0
0
Slave receive mode
1
Slave transmit mode
1
0
Master receive mode
1
Master transmit mode
Note: * For details see section 18.2.5, I
Control Register.
2
1
BBSY
IRIC
0
0
R/W
R/(W)*
Start condition/stop condition prohibit
0 Writing 0 issues a start or stop condition,
in combination with the BBSY flag
1 Reading always returns a value of 1
Writing is ignored
2
C Bus interface interrupt request flag
0 Waiting for transfer, or transfer in progress
1 Interrupt requested
Control Register.
2
C Bus
IIC0
IIC1
0
SCP
0
R/W
2
C Bus
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